`include "ascon_define.v"

module `SINGLE_BIT_ANY_CYC
    #(
     parameter CYC_N                             = 1
     )
     (
     input                                       clk_i,
     input                                       rst_n_i,
     input                                       en_i,
     input                                       dat_d_i,

     output                                      dat_q_o,
     output                          [CYC_N-1:0] vld_o
     );

reg                                          en_r;
wire                                         en_neg_w;

reg                                  [1-1:0] d_rag [CYC_N-1:0];

assign dat_q_o          = d_rag[CYC_N-1];

assign en_neg_w         = (~en_i)&en_r;

always @(posedge clk_i or negedge rst_n_i)
begin : EN_R_PROG
  if (rst_n_i == 1'b0)
    en_r                <= 1'b0;
  else
    en_r                <= en_i;
end

genvar index;

generate

for (index = 0 ; index < CYC_N;index = index + 1 )
begin : D_RAG_LOOP
if (index == 0)
begin
always @(posedge clk_i or negedge rst_n_i)
begin : D_RAG_PROG
  if (rst_n_i == 1'b0)
    d_rag[index]        <= 1'b0;
  else if (en_neg_w == 1'b1)
    d_rag[index]        <= 1'b0;
  else if(en_i == 1'b1)
    d_rag[index]        <= dat_d_i;
  else
    d_rag[index]        <= d_rag[index];
end

assign vld_o[index]     = dat_d_i;

end

else

begin

always @(posedge clk_i or negedge rst_n_i)
begin : D_RAG_PROG
  if (rst_n_i == 1'b0)
    d_rag[index]        <= 1'b0;
  else if (en_neg_w == 1'b1)
    d_rag[index]        <= 1'b0;
  else if(en_i == 1'b1)
    d_rag[index]        <= d_rag[index-1];
  else
    d_rag[index]        <= d_rag[index];
end

assign vld_o[index]     = d_rag[index-1];

end



end


endgenerate

endmodule